1. Field of the Invention
Embodiments of the invention relate to amplification circuits adapted for use in semiconductor devices. More particularly, embodiments of the invention relate to a duty cycle correction amplification circuit.
This application claims priority to Korean Patent Application No. 2005-122488 filed Dec. 13, 2005, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Various types of amplification circuits are routinely used in semiconductor devices. Generally speaking, an amplification circuit outputs an amplified signal corresponding to an input reference signal. Many of the signals subjected to amplification in a semiconductor device are periodic in nature and characterized by co-called duty cycle. “Duty cycle” is a well known term and generally defines a ration between “ON time” and “OFF time” for a particular signal. ON time, for example, may be defined as a period during which the signal is in a logically high state. The duty cycle of a signal is an important performance characteristic, and related circuit operation is often defined in relation to it. Unfortunately, the duty cycle of a signal may become distorted by numerous factors.
As a result, conventional amplification circuits have been developed that correct duty cycle distortion as well as amplify the signal. For purposes of this description, an amplification circuit having a duty cycle correction capability will be referred to as a “duty cycle correction amplification circuit”.
FIG. (FIG.) 1 is a circuit diagram illustrating a conventional duty cycle correction amplification circuit. The duty cycle correction amplification circuit of FIG. 1 includes a first amplifier 10, a second amplifier 20, and a duty cycle corrector 30. First amplifier 10 generates first and second preliminary signals VPRE and VPREB corresponding to received first and second reference signals VREF and VREFB. Second amplifier 20 generates an amplified output signal VOUT based on the first and second preliminary signals VPRE and VPREB. The output signal VOUT is buffered by a buffer 40, which may be implemented using an inverter. The amplified signal output from buffer 40 is termed VAMP. Duty cycle corrector 30 adjusts current supplied to the first and second preliminary signals VPRE and VPREB, thus correcting the duty cycle of the output signal VOUT, and ultimately, the duty cycle of amplified signal VAMP.
In the conventional duty cycle correction amplification circuit of FIG. 1, duty cycle corrector 30 is connected to the first and second preliminary signals VPRE and VPREB. In this configuration, current flows from the first and second preliminary signals VPRE and VPREB to duty cycle corrector 30 to correct the duty cycle of the amplified signal VAMP. Due to this current flow, the voltage levels of the first and second preliminary signals VPRE and VPREB may be reduced. As a result, the voltage margin for proper operation (e.g., within a defined saturation region) of NMOS differential input transistors 11 and 13 may be impaired and the amplification factor of the circuit decreased accordingly. Further, the operating speed of the duty cycle correction amplification circuit may decrease, since it becomes increasingly difficult to operate the duty cycle correction amplification circuit at lower voltages. Still further, due to the load capacitance of duty cycle corrector 30, the frequency characteristics of the amplified signal may deteriorate.
Consequently, the conventional duty cycle correction amplification circuit is problematic in that the amplification factor and operating speed of the circuit may be impaired under certain operating conditions.